In flip chip processing of semiconductor integrated circuit (IC) chips, interconnect structures such as solder bumps are used to connect IC dies to packaging. However, due to the coefficient of thermal expansion (CTE) differences between the IC die and the packaging, solder bumps can experience large stresses at interconnect joints positioned therebetween and thereby cause a risk of crack formation during the joining of a chip. In addition, CTE mismatch can cause strains on the material during cooldown and solder solidification processes. A mismatch between CTEs may be especially prevalent, e.g., where interconnects include solder, copper pillars, and/or similar materials which join a silicon chip to a substrate such as a circuit board or other element composed of ceramic, leadframe, and/or other materials. Corrective designs for mitigating these risks may be insufficient because substrate and laminate materials must also match with a particular map of interconnects at room temperature, even though these elements are joined together under higher temperature conditions.